Computer Architecture and Design

EECE.4821/5821 Computer Architecture and Design

Credits: 3

Contact Hours: 3 hours of lecture

Instructor: Seung Woo Son

Textbook: David A. Patterson and John L. Hennessy, Computer Organization and Design MIPS Edition: The Hardware/Software Interface, 5th edition, 2013, ISBN: 9780124077263

Other supplemental materials: All supplemental materials can be found on the UMass Lowell Blackboard portal ( These materials include lecture slides, handouts, recordings, assignments, quizzes, and other documentation.

Course Catalog Description: Structure of computers, past and present: first, second, third and fourth generation. Combinatorial and sequential circuits. Programmable logic arrays. Processor design: information formats, instruction formats, arithmetic operations and parallel processing. Hardwired and microprogrammed control units. Virtual, sequential and cache memories. Input-output systems, communication and bus control. Multiple CPU systems.

Prerequisites: EECE.2650 (Logic Design) and EECE.3170 (Microprocessors I).

Grading: Attendance or in-class quizzes (10%), Written or lab assignments (50%), Midterm exam (20%), Final exam (20%)

Required or elective? This course is required for Computer Engineering majors while Electrical Engineers may use it as a technical elective.

Course Outcomes:

By the end of this course, students will understand and be able to use all of the following:

  1. Performance: measuring CPU performance in terms of execution time.
  2. Instruction Set Architecture: Operations and operands of computer hardware, MIPS instruction set.
  3. Computer Arithmetic: Addition and subtraction, multiplication, division, floating point arithmetic.
  4. Processor: Building datapath, pipelined datapath and control, data and control hazards, instruction-level parallelism.
  5. Memory Hierarchy: memory technologies, cache memory, virtual memory, cache coherence
  6. I/O: disk and storage class memory, I/O interfaces, RAID (redundant arrays of inexpensive disks).
  7. Parallel Processors: SISD, MIMD, SIMD, SPMD, and Vector, hardware multithreading, shared and distributed memory multiprocessors, GPUs, multiprocessor network topologies.

Course Topics

  • Computer abstractions and technology: computer architecture revolution underpinned by Moore’s law
  • Performance metric: measuring CPU performance, execution time, cycle per instruction (CPI), clock cycle, power wall
  • MIPS ISA: signed/unsigned numbers, instruction representations, logical operations, branch instructions, procedure support in hardware, addressing modes, parallelism and synchronizations
  • Computer Arithmetic: integer addition/subtraction/multiplication/division, IEEE 754 floating point number, number conversion, subword parallelism
  • Datapath: building a single-cycle datapath, pipelined datapath and control, data hazards, stalls and forwarding, control hazards, speculation, exceptions, out-of-order execution, static and dynamic multiple issue
  • Cache memory: memory technologies, locality, directed-mapped cache, measuring cache performance, associativity, cache control state machine, cache coherence
  • Virtual memory: virtual machine, virtual to physical address translation, translation-lookahead buffer
  • I/O subsystems: redundant array of inexpensive disks, distributed parity
  • Multiprocessors: strong and weak scaling, SIMD, vector machine, hardware multithreading, graphical processing unit, loosely and tightly coupled machine


Note that below is a tentative schedule based on 14 meetings.

Week Topic Reading Assignment
1 Syllabus; Course overview and performance metric Chapter 1
2 MIPS ISA 1/2 Chapter 2 Lab 1 out
3 MIPS ISA 2/2 Chapter 2
4 Arithmetic, floating-point Chapter 3 Lab 1 due; Lab 2 out
5 Datapath and control Chapter 4.1~4.4
6 Pipelined datapath, data and control hazards; midterm exam review Chapter 4.5~4.9 Lab 2 due; Lab 3 out
7 Midterm exam
8 Review midterm solution; MIP multiple issue (superscalar) model Chapter 4.10~4.14 Lab 3 due; Lab 4 out
9 Memory hierarchies and cache basics Chapter 5.1~5.3
10 Improving cache performance, cache coherence Chapter 5.4,5.8~5.15
11 Virtual memory Chapter 5.7 Lab 4 due; Lab 5 out
12 IO subsystems Chapters 1.4, 4.9, 5.2, 5.5, 5.11, 6.9 Paper review draft due
13 Multiprocessor Chapter 6 Paper review due
14 GPU Lab 5 due
Final exam (exam week)