Contact Hours: 3 hours of lecture
Instructor: Seung Woo Son
Textbook: David A. Patterson and John L. Hennessy, Computer Organization and Design MIPS Edition: The Hardware/Software Interface, 5th edition, 2013, ISBN: 9780124077263
Other supplemental materials: All supplemental materials can be found on the UMass Lowell Blackboard portal (https://www.uml.edu/blackboard/). These materials include lecture slides, handouts, recordings, assignments, quizzes, and other documentation.
Course Catalog Description: Structure of computers, past and present: first, second, third and fourth generation. Combinatorial and sequential circuits. Programmable logic arrays. Processor design: information formats, instruction formats, arithmetic operations and parallel processing. Hardwired and microprogrammed control units. Virtual, sequential and cache memories. Input-output systems, communication and bus control. Multiple CPU systems.
Prerequisites: EECE.2650 (Logic Design) and EECE.3170 (Microprocessors I).
Grading: Attendance or in-class quizzes (10%), Written or lab assignments (50%), Midterm exam (20%), Final exam (20%)
Required or elective? This course is required for Computer Engineering majors while Electrical Engineers may use it as a technical elective.
By the end of this course, students will understand and be able to use all of the following:
Note that below is a tentative schedule based on 14 meetings.
|1||Syllabus; Course overview and performance metric||Chapter 1|
|2||MIPS ISA 1/2||Chapter 2||Lab 1 out|
|3||MIPS ISA 2/2||Chapter 2|
|4||Arithmetic, floating-point||Chapter 3||Lab 1 due; Lab 2 out|
|5||Datapath and control||Chapter 4.1~4.4|
|6||Pipelined datapath, data and control hazards; midterm exam review||Chapter 4.5~4.9||Lab 2 due; Lab 3 out|
|8||Review midterm solution; MIP multiple issue (superscalar) model||Chapter 4.10~4.14||Lab 3 due; Lab 4 out|
|9||Memory hierarchies and cache basics||Chapter 5.1~5.3|
|10||Improving cache performance, cache coherence||Chapter 5.4,5.8~5.15|
|11||Virtual memory||Chapter 5.7||Lab 4 due; Lab 5 out|
|12||IO subsystems||Chapters 1.4, 4.9, 5.2, 5.5, 5.11, 6.9||Paper review draft due|
|13||Multiprocessor||Chapter 6||Paper review due|
|14||GPU||Lab 5 due|
|Final exam (exam week)|